In attempting to use the area on printed wiring boards (PWB) and printed circuit boards (PCB) more efficiently, semiconductor chip manufactures have been switching from larger, more cumbersome interconnection techniques, such as pin grid arrays (“PGAs”) and perimeter leaded quad flat packs (“QFPs”), to smaller assemblies, such as ball grid arrays (“BGAs”). Using BGA technology, semiconductor chips are typically interconnected to their supporting substrates using solder connections. However, the columns of solder are generally designed to be relatively short to maintain the solder's structural integrity, which reduces elastic properties, resulting in,increased susceptibility to solder cracking due to a differential between the coefficient of thermal expansion (“CTE”) of the chip relative to the CTE of the supporting substrate. Thus, as the chip heats up during use, both the chip and the substrate expand; and when the heat is removed, both the chip and the substrate contract. The difference between the chip CTE and the substrate CTE can result catastrophic deformation.
Therefore, the ability to dissipate heat that is generated from the operation of integrated circuits (IC) is a major design concern for the electronic industry. This is emphasized because the density of circuits on IC devices has increased substantially in recent years and the reliability and performance of these high density circuits are affected by the thermal environment. Additionally, size considerations require that an increased number of electronic packages be installed into very small spaces, which also greatly increases the need to efficiently dissipate heat from IC packages. As the features of semiconductor chips continue to be reduced in size, the number of chips packed into a given area will be greater and the heat dissipated by the each of these chips will have a greater effect on the thermal mismatch problem discussed above.
Furthermore, IC devices are increasingly being used for high power applications. While many early IC chips operated below a few watts, ICs are being designed to operate around 10 watts, which substantially increases heat generation and the need to effectively dissipate the heat.
In some conventional semiconductor packages, heat generated from a semiconductor chip or integrated circuit (IC), which is typically mounted on a die pad of a substrate, is emitted through two routes. The first route is through external connection terminals of the package and the second route is through the surface of the package. In order to more effectively dissipate the heat, a heat sink can be attached to the package. In a ball grid array (BGA) package, which includes an encapsulating resin formed by molding a semiconductor chip with a plastic resin, the heat sink may be attached directly to the encapsulating resin of the package. Thus, the heat generated from the chip is conducted to the heat sink via the encapsulant and dissipated to the outside by convection.
Other approaches to solve the problem of heat dissipation include adding additional thermal balls under the die area. However, this approach requires modification of the package design and possibly a layout change as well as possible modification of the PWB or PCB design. Another approach is to modify the package type and/or reduce the required power. These approaches are not satisfactory since they require major design changes.
Bourdelaise et al. disclose in U.S. Pat. No. 5,027,191, a chip carrier assembly utilizing a cavity down chip with a pad grid array. The IC chip within the chip carrier is mounted against a surface opposite the PWB to which the chip is attached such that heat transfer from the IC chip may occur along a short path to a heat sink to enable a larger heat transfer rate. The improvement of heat transfer rate is still quite limited due to a small gap that is usually required on the top surface of an IC chip to allow bonding wires to extend from the chip to connection pads surrounding the chip. This small gap between the IC chip and the flat thermal pad serving as a heat sink substantially reduces the heat transfer rate.
Huang et al. disclose in U.S. Pat. No. 6,525,942, a heat dissipation ball grid array (BGA) package. The heat dissipation BGA package includes a plurality of first thermal ball pads formed on the underside of a substrate in the area covered by a chip. The BGA package also includes a plurality of second thermal ball pads or a heat dissipation ring outside the first thermal ball pads. A plurality of signal ball pads is formed outside the second thermal ball pads or the heat dissipation ring. The second thermal ball pads or heat dissipation ring is connected to the first thermal ball pads by conductive trace lines. A plurality of first thermal balls is attached to the respective first thermal ball pads and the signal balls are attached to the respective signal ball pads. The first thermal balls and the signal balls are in contact with corresponding contact points on a printed circuit board. A plurality of second thermal balls is attached to the respective second thermal ball pads or the surface of the heat dissipation ring. The heat dissipation disclosed in Huang is limited because the die pad conducts thermal energy to the first and second thermal balls only through the vias.
Chao et al. disclose in U.S. Pat. No. 6,483,187, a heat spread substrate that includes a metal heat spreader, which has a surface with a cavity that is adapted to support a die. The surface also includes a ground ring arranged at the periphery of the cavity, a substrate-supporting surface surrounding the periphery of the ground ring, a plurality of ground pads arranged at the periphery of the substrate-supporting surface and a plurality of ground pads arranged on the substrate-supporting surface and protruding from it. The substrate also has a plurality of through holes, a plurality of mounting pads and a plurality of ball pads. Chao discloses that a thickness decreasing process is carried out on one of the surfaces of the metal heat spreader to decrease the thickness of part of the areas on the surface. The thickness decreasing process can be accomplished by stamping processes, or by multi-photolithography and half-etching. One drawback to varying the thickness of the heat spreader to dissipate heat is that it requires specific fabrication steps to produce the desired heat spreader shape.
With the above limitations and difficulties, there is still a need in the art of IC packaging techniques to resolve these difficulties and limitations. Specifically, there is a need in the art to provide improved heat dissipation for high power ICs and meanwhile increase the packaging integrity.